Flip-flop circuit elements are known and widely used in VLSI integrated circuit (IC) design. Flip-flop circuit elements act as digital storage devices, receiving digital data (logic 1 or 0) at their input, storing the digital data and then providing the stored digital data as output when queried. These tasks of receiving, storing and generating output are synchronized by a clock signal.
Depending upon the application, the clock signal may have a frequency of from several megahertz to several Gigahertz. In typical operations, a flip-flop receives data when the clock signal is either low or high, stores the data when the clock signal transitions from low to high or vice versa and generates its output during the clock signal's high or low state.
All flip-flop activity consumes power. Given that the clock runs continuously, the power consumption by flip-flops accounts for a very significant portion of the entire IC's power consumption. As the frequency of operation and complexity of ICs is likely to increase as IC feature size shrinks, the power consumption of flip-flop circuit elements is also likely to increase significantly.
The total power consumption for any given complementary metal oxide semiconductor (CMOS) IC can be stated as:
 Ptotal=Pact+Psc+Pleak;
where
    Ptotal is the total power consumed by the CMOS IC;    Pact is the power consumed during switching activity (this is the major component of total power consumption);    Psc is the power consumed by short circuit currents. These current flow from power supply to ground when gate inputs transition (typically these are a minor component of total power consumption and will not be discussed further); and    Pleak is the power consumed by leakage currents (these currents are process related, usually a negligible component of total power consumption and require no further discussion here).
For flip-flop circuits, Pact has two components. These are:Pact=Pclk+Pdata;where    Pclk represents the power consumption due to clock switching activity; and    Pdata represents the power consumption due to data switching activity.
In turn, both Pclk and Pdata can be further defined as:Pclk=(Cclk*V2*freq);andPdata=(Cdata*V2*freq)*AF;where    Cclk is the total charging and discharging capacitance of the clock signal;    Cdata is the total charging and discharging capacitance of the data signal;    freq is the clock frequency;
AF is the average data activity factor and typically has a value of from 5 to 10%; and    V is the operating voltage.
In most applications, the average data activity factor (AF) is about 10% of the clock frequency. Consequently, a majority of the power consumption in a flip-flop circuit is consumed by clock switching. As the clock operates continuously, the activity factor of clock switching is 100%.
Although one method for reducing the power consumption is to reduce the operating voltage, this reduction typically results in less reliable operation, as operating margins are reduced. Reducing the switching capacitance that is controlled or triggered by the clock signal and the short circuit current of the clock is thus the most direct method of reducing power consumption in a flip-flop circuit.
A flip-flop design that limits the amount of clock capacitance and short-circuit current without affecting the flip-flop's performance would be highly desirable.